Senior SoC/ASIC Physical Design Engineer

Job Summary

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and implementing flow, methodologies, and the physical implementation of state-of-the-art SoCs to optimize the design for performance, power efficiency, and area.

Technical Qualifications

• 5+ years of ASIC and/or physical design flow development experience
• Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools).
• Scripting experience with Python, Tcl, or Perl
• Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation.
• Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
• Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
• Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
• Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

Key Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Other Requirements

• Passion for learning new technologies
• Taking pride in always producing high quality code and documentation
• Excellent communication skills
• Comfortable and willing to work with team members from different disciplines, different levels and across time-zones